US EPA

3011609 

Journal Article 

Study of Thermally Enhanced 2.5D Packages with Multi-chips Molded on Silicon Interposer 

Zhang, HY; Zhang, XW 

2015 

Yes 

Journal of Electronic Materials
ISSN: 0361-5235
EISSN: 1543-186X 

44 

7 

2396-2405 

10.1007/s11664-015-3715-7 

WOS:000355656000023 

The 2.5D package with distributed vias on silicon interposer has received great attention due to its potential for heterogeneous integration. The overmolded 2.5D package protects the silicon die and interposer from environmental damage, which, on the other hand, induces undesirable thermal resistance due to low thermal conductivity of the molding compound. In this paper, a thermally enhanced 2.5D package with exposed die is proposed, fabricated and examined from the thermal enhancement viewpoint. The high power thermal test die was first assembled on a silicon interposer with through silicon vias and connected to the substrate, which was followed by the overmolding and back-grinding processes to form the partially molded (PM) package with exposed die for direct heat sink attachments. Experiments were conducted to examine the thermal performance under different thermal conditions. Under natural convection without thermal enhancement, there was no performance difference between the PM package and the overmolded package. However, when the package top was mounted with a thermally enhanced structure such as a pin fin heat sink, the thermal resistance of PM package was significantly reduced. The advantage was more prominent with the attachment of a high performance liquid cooling heat sink. Thermal simulation models were also constructed to examine the thermal performances under different test conditions, and the realistic thermal interface resistance of 0.5 Kcm(2)/W was estimated based on the package warpage. The computed thermal resistances agreed with measurement results. 

Thermal enhancement; partial mold (PM); 2.5D package; through silicon via (TSV); thermal simulation; thermal interface material; pin fin heat sink