Health & Environmental Research Online (HERO)


Print Feedback Export to File
326862 
Journal Article 
Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs : Wafer-level packaging 
Chow, EM; Fork, DK; Chua, CL; Van Schuylenbergh, K; Hantschel, T 
2009 
32 
2 
372-378 
Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm × 6.5 mm with 48 spring contacts on a 0.8 mm × 0.65 mm grid array, each spring measuring 400 μm ×x 100 μm. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20000 hot plate thermal cycles and > 1000 oven thermal cycles without failure. (English) 
Cantilever; compliant interconnects; fine pitch; flip chip; memory packaging; micro-spring; probing; stress-engineered; surface mount technology; wafer level packaging; Fabrication microélectronique; Circuit imprimé; Circuit intégré; Assemblage circuit intégré; Poutre cantilever; Métal fondu brasage tendre; Couche mince; Défaillance; Cycle thermique; Brasage sans plomb; Brasage avec refusion; Sérigraphie; Montage surface composant; Essai thermique préliminaire; Pastille électronique; Métallisation; Carte électronique; Matrice formage; Interconnexion; Puce à bosses; Packaging électronique; Essai circuit intégré; Assemblage brasage tendre; Technologie CSP; Microelectronic fabrication; Printed circuit; Integrated circuit; Integrated circuit bonding; Cantilever beam; Solder metal; Thin film; Failures; Thermal cycle; Lead free soldering; Reflow soldering; Serigraphy; Burn in test; Wafer; Metallizing; Printed circuit board; Die; Interconnection; Flip-chip; Electronic packaging; Integrated circuit testing; Soldered joint; Chip scale packaging; Fabricación microeléctrica; Circuito imprimido; Circuito integrado; Viga cantilever; Metal fundido soldeo blando; Capa fina; Fallo; Ciclo térmico; Soldeo sin plomo; Soldeo con refusión; Serigrafía; Montaje superficie componente; Prueba térmica preliminar; Pastilla electrónica; Metalización; Tarjeta electronica; Matriz formadora; Interconexión; Packaging electrónico; Junta soldada