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7110022 
Journal Article 
Failure analysis of stacked-chip scale package 
Flores, CC; , 
2000 
ASM INTERNATIONAL 
MATERIALS PARK 
333-337 
Stacked-chip scale package (S-CSP) is a new packaging technology introduced in the memory components market to effect chip miniaturization, a challenging trend in semiconductor assembly. The package is built by molding two stacked dice (Flash and SRAM) on bismaleimide triazine (BT) substrate. As this novel packaging technology offers solution to the challenge, it also poses complexity in the field of failure analysis in cases that the bottom die is the interest.Deprocessing these stacked dice while maintaining the functionality of the bottom die will be explained in detail. Prior the conduct of failure analysis (FA) and fault isolation (R), deprocessing the failing unit containing only one die normally consists of chemical decapsulation. S-CSP sample preparation also adheres to this treatment in case the top die is the aim for analysis. On the other hand, if the concerti shifts to the bottom die, sequential techniques involving precision polishing to die-to-die adhesive layer, chemical etching of adhesive and residual molding compound, and rebonding the bottom die on ceramic interposer, are employed. With the rebonded S-CSP bottom die, fault isolation could be pet-formed further.This paper will also feature the mechanism behind the blown-up failure, a power test failure in memory devices, encountered during the package development when two types of die-to-die adhesives were selected and used. Consistent with the results of electrical characterization suggesting that S-CSP bottom die as the failing die, passivation damage is uncovered on the bottom die upon separation of the stacked dice. Material comparison points out that the hard, angular glass fillers of the die-to-die adhesive induce the damage. Polymer-filled adhesive performs better than the glass-filled adhesive as indicated by the results of the package characterization. Generally, this case exemplifies a packaging material-related failure.Moreover, the paper could serve as a reference material in the event that feasibility of packaging non-memory components in S-CSP is to be evaluated. The developed methodology of recovering the S-CSP bottom die would be a keystone in proacting for its FA readiness. 
0-87170-701-2 
26th International Symposium for Testing and Failure Analysis 
BELLEVUE, WA