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HERO ID
7042522
Reference Type
Journal Article
Title
Development of Die-bonder with Multi & Matrix Picker and Placer to Increase Production Capacity
Author(s)
Kim, P; Ha, Y; Park, H; Park, J; ,
Year
2012
Publisher
INT ASSOC ENGINEERS-IAENG
Location
HONG KONG
Page Numbers
369-371
Web of Science Id
WOS:000398979600065
Abstract
In Back-End process of semiconductor manufacturing, Die-Bonding is one of the process that bond chips on wafer to PCB(Plastic Circuit Board). Due to the nature of the rapidly changing semiconductor industry, production speed is one of the most important topic. Therefore, A machine equipped with MMPP(Multi-Matrix Picker and Placer) was developed. P&P(Picker and Placer) is a part of machine that pick and place a die, it is the most essential parts in Die-Bonder. In case of existing machine, it has a P&P that grab a die from wafer, then translate to position of PCB and attach the die on it. In this study, the machine with MMPP(Multi and Matrix Picker and Placer) was developed to increase UPEH(Unit Per Equipment Hour). This developed machine has 2 P&P. They grab the die, then move to position of PCB and attach all die on it. And each P&P has 6 collect which directly contact with the die. Therefore it can grab 6 die without bonding. The advantage of this method is that it reduced the time to move between PCB and Wafer and increased UPEH by 2.1 times using Multi-P&P compared to existing method SOPP(Single One Picker and Placer). It was measured by producing 16Gb-MLC(Multi Level Cell)-nand flash in all experiments. This new structure of MMPP was applied to the machine but it was designed to keep the same size with existing one. The authors describe layout of the machine and performance properties and discusses the analysis of productivity growth and accuracy based on experimental results. It was confirmed that UPEH of the machine with MMPP is 2.1 times than S-300 that is existing machine and accuracy is the same in both machine.
ISBN
978-988-19251-6-9
Conference Name
World Congress on Engineering and Computer Science
Conference Location
San Francisco, CA
Tags
IRIS
•
PCBs
Litsearches
WOS
2020 Restored References_Dec 2023
Restored references_April 2024
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