US EPA

2151422 

Book/Book Chapter 

Thermal efficient three dimensional semiconductor packages for high performance processor modules 

Ahearn, W 

1998 

IMAPS 

Berlin, Reston, VA 

1998 International Symposium on Microelectronics 

3582 

726-731 

English 

WOS:000078815800123 

A new family of semiconductor packages, referred to as VSPA (TM), is described that combines unique 3D design features and materials technology selection to produce superior electrical, thermal and mechanical performance for both single and multiple chip modules. These packages are readily scaleable to accommodate a wide variety of footprint, shape, I/O (up to 1000) and bandwidth requirements at very low cost ($.01). The unique design and fabrication method eliminates the die leadframe allowing a smaller footprint, relaxed lead pitch, and robust leads with improved coplanarity. The I/O pins are a constant regardless of the package frame size which provides a low inductance path from the die to the PCB. The peripheral lead structure allows for visual inspection and ease of rework. The die attaches in a flip chip manner to a metallic plate, an integral part of the package, providing a direct thermal path to ambient or cooling devices.


The 3D stacking of the leads results in significant size reduction, low inductance paths, with the pin design providing reduced package parasitics allowing resonance free operation up to 3.5 GHz. Techniques for the 3D stacking of chips are described as well as environmental test results, standard activity, and novel headsink designs. A liquid crystal polymer frame provides excellent stability with a 335 degrees C melt point, allows for tolerances of less than I mil to be held for pin alignment and coplanarity in high volume manufacturing environments. 

Proceedings of the Society of Photo-optical Instrumentation Engineers (SPIE) 

0930815521 

1998 International Symposium on Microelectronics 

San Diego, CA 

November 01-04, 1998