Kaviani, K; Wu, T; Wei, J; Amirkhany, A; Shen, Jie; Chin, TJ; Thakkar, C; Beyene, WT; Chan, N; Chen, C; Chuang, B; Dressler, D; Gadde, VP; Hekmat, M; Ho, E; Huang, C; Phuong Le; Mahabaleshwara; Madden, C; Mishra, NK; Raghavan, L; Saito, K; Schmitt, R; Secker, D; Shi, X; Fazeel, S; Srinivas, GS; Zhang, S; Tran, C; Vaidyanath, A; Vyas, K; Jain, M; Chang, K; Yuan, X
This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3 '' FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package change. The compact, low-power and high-speed tri-modal interface is enabled by substantial reuse of the circuit elements among various signaling modes, particularly in the wide-band clock generation and distribution system and the multi-modal driver output stage, as well as the use of fast equalization for post-cursor inter-symbol interference (ISI) mitigation. In the high-speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE operation to the memory. In contrast, during a memory READ operation, it employs a linear equalizer (LEQ) with 3 dB of peaking as well as a calibrated high-speed 1-tap predictive decision feedback equalizer (prDFE), while no transmitter equalization is assumed for the memory. The prototype tri-modal interface implemented in a 40-nm CMOS process, consists of 16 data links and achieves more than 2.5 x energy-efficient memory transactions at 16 Gbps compared to a previous single-mode generation.