US EPA

2181870 

Journal Article 

Current-Mode Echo Cancellation for Full-Duplex Chip-to-Chip Data Communication 

Rao, VSP; Mandal, P 

2010 

748-751 

WOS:000296009300189 

In this paper we propose current-mode echo cancellation technique for full-duplex chip-to-chip data communication. A new hybrid circuit topology suitable for current-mode echo cancellation is presented. The hybrid circuit topology is shared integration of an operational transconductance amplifier(OTA) and a transimpedance amplifier(TIA). The output/back-port impedance of the hybrid is matched with the characteristic impedance of the transmission line. The proposed topology separates the inbound wave from the received wave, which is a superposition of inbound and outbound waves. The proposed hybrid is implemented in 1.8-V, 0.18-mu m Digital CMOS technology with BSIM3v3 models which take into account device parasitic and second order effects. The simulated performance shows 4-Gb/s data transfer rate over a 7.5-inch FR4 PCB trace with the proposed hybrid circuit on both the ends of the line. The 7.5-inch FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100-MHz to 20-GHz. The power consumed in the hybrid 10.64-mW. The output noise voltage of OTA and input-referred noise current of TIA are 4.32mV and 1.52-mu A respectively. The targeted bit-error rate(BER) of the link is 10(-12). 

full-duplex; chip-to-chip interconnect; current-mode; transimpedance amplifier; hybrid