US EPA

2935574 

Journal Article 

Linearization of CMOS Cascode Power Amplifiers Through Adaptive Bias Control 

Jin, S; Park, B; Moon, K; Kwon, M; Kim, B 

2013 

Yes 

I E E E Transactions on Microwave Theory and Techniques
ISSN: 0018-9480 

61 

12 

4534-4543 

10.1109/TMTT.2013.2288206 

WOS:000327952100054 

Highly linear and efficient CMOS cascode power amplifiers (PAs) are developed for handset applications. The linearity of the PAs is improved using adaptive bias circuits at the gates of the common-source (CS) and the common-gate (CG) stages. The memory effects that are generated by the bias circuits are reduced using second harmonic control circuits at the source of the CS and the gate of the CG stages. The proposed PA, including the integrated bias circuits, is fabricated using a 0.18 - mu mRF CMOS technology. The adaptive gate bias circuits improve the linearity and efficiency significantly. The measurement results show that the side-band asymmetry is less than 1.5 dB and the peak average power is improved by 1.2 dB within the linearity specification for a 16-QAM 7.5 dB PAPR LTE signal. The bias circuits improve the linearity of the PA within the specification without using digital pre-distortions. The CMOS PA delivers a power-added efficiency (PAE) of 41.0%, an error vector magnitude (EVM) of 4.6%, and an average output power of 27.8 dBm under an ACLR(E-UTRA) of -31.0 dBc for a 10-MHz bandwidth signal at 1.85-GHz carrier frequency. 

ACLR asymmetric; adaptive bias circuit; AM-to-AM; baseband injection; bias circuit; cascode; class-AB; CMOS; common-gate; deep class-AB; differential; envelope injection; IMD asymmetry; inter-modulation distortion (IMD); linear power amplifier; linearity; linearization; long term evolution (LTE); low quiescent current; memory effect; PCB transformer; power amplifier (PA); transmission line transformer (TLT)